Multi-core microprocessors require many clock domains and hence many phase locked loops (PLL). The jitter requirements for PLL's on multi-core microprocessors are much more stringent, requiring a sigma jitter of 1.5 ps, compared to the standard 5-8 ps jitter typically associated with PLLs presently used. One possibility to achieve such a low jitter is to use an inductive-capacitive (LC) PLL. However, this requires the process to incorporate integrated inductors, which adds significant cost and complexity to the manufacturing. In addition, the LC PLLs have a very thin tuning range, which disqualifies them in many applications which require banding. Transistor-based low jitter PLL's have been suggested, but require on chip voltage regulators (VR) which have very low noise characteristics, referred to as low-noise voltage regulators (LNVR).
When there are many PLLs and VRs present on chip, the impedance of the VRs as seen from the analog power supply pin can cause the LC network on the package to oscillate. In digital microprocessor chips, the package network of the analog supply typically has much less supply traces than the digital supply. This may cause a relatively high inductance at this supply, namely several nH. For many VRs the phase of the impedance seen from the supply pin will become >90 degrees near the bandwidth of the VR (e.g., 100-200 MHz) which will cause negative real impedance. If the frequency that the impedance crosses from positive to negative is in the resonant range of the LC network (e.g., <500 MHz) and the inductance of the LC network is high enough, then oscillations can occur.